I'm super happy that my latest chip Greyhound has been accepted for production! 
It was designed with open source EDA tools and the IHP Open Source PDK.
Find out more here: https://github.com/mole99/greyhound-ihp
And down below 
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The Spade Hardware Description Language - Spade is an open-source hardware description language (HDL) developed at Linköping... - https://hackaday.com/2025/04/13/the-spade-hardware-description-language/ #hardwaredescriptionlanguage #spadelanguage #hardware #verilog #fpga #asic #vhdl #hdl
Hackaday · The Spade Hardware Description LanguageSpade is an open-source hardware description language (HDL) developed at Linköping University, Sweden. Other HDLs you might have heard of include Verilog and VHDL. Hardware engineers use HDLs to de…
Active Super ordered to pay $10.5 million penalty in ASIC’s third greenwashing court action
asic.gov.au25-042MR Active Super ordered to pay $10.5 million penalty in ASIC’s third greenwashing court action | ASICFair, strong and efficient financial system for all Australians.
Oh falls ihr wegen der Arbyte oder wegen Toy Projekt weg von Asien und US Silizium kommen wollt, schaut Euch mal den #cva6 an: Ist ne 6-stage pipeline #riscv (32/64bit) Implementierung die #fpga und #asic ready und gut verifiziert ist. Basiert auf der Arbeit der ETH Zürich, wurde dann von Thales aus Frankreich weiter entwickelt und wird nun durch die OpenHW Group betreut - also nen echtes Europa Dings:
GitHubGitHub - openhwgroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting LinuxThe CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux - openhwgroup/cva6
Last few days for Tiny Tapeout 10!
The shuttle closes at 21:00 CET / 12:00 PT on Monday 10th of March.
We have some great projects on board already, including 3.3v mixed signal analog, a bandgap reference, the demoscene competition entries and RISCV SoCs.
But we want even more, so put on your ASIC hat and get that last minute design submitted onto Tiny Tapeout 10!
It's time for another YUG! What's a YUG? It's the Yosys User's Group! For anyone interested in using Yosys - we've had sessions on primitives, plugins, hardware security, FPGAs and lots more...
This time we'll be turning to #ASIC synthesis with our own Emil Jiří Tywoniak. @the_art_of_giving_up
Tiny Tapeout 10 demoscene competition is open! Enter for free and win some great prizes!
Quicker, easier and cheaper to make your own chip!TT10 Demoscene - Tiny TapeoutBuild a sound and graphics demo in less than 161 x 225 microns of 130nm ASIC
A Tiny Tapeout SDR https://hackaday.com/2025/02/11/a-tiny-tapeout-sdr/ #tinytapeout #RadioHacks #Parts #ASIC #sdr
Hackaday · A Tiny Tapeout SDRThe Tiny Tapeout custom ASIC project has been around for a while now, and has passed through several iterations of its production. On each Tiny Tapeout chip are multiple designs, each representing …
A Tiny Tapeout SDR - The Tiny Tapeout custom ASIC project has been around for a while now, and has pass... - https://hackaday.com/2025/02/11/a-tiny-tapeout-sdr/ #tinytapeout #radiohacks #parts #asic #sdr
Hackaday · A Tiny Tapeout SDRThe Tiny Tapeout custom ASIC project has been around for a while now, and has passed through several iterations of its production. On each Tiny Tapeout chip are multiple designs, each representing …
Don't miss my next open source silicon stream!
As well as the latest news and events I'll be looking at some new silicon proven designs and look at reading and writing via SPI.
Anyone know if there is #OpenHardware #ASIC production or even specification somewhere?
I found resources online: https://github.com/mattvenn/awesome-opensource-asic-resources/blob/main/README.md but not exactly what I'm looking for.
Continued thread
Custom shaders are working on my Tiny Tapeout 06 project "Tiny Shader"! 
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The video shows the VGA output on a monitor, each shader uses up to 10 instructions. There's a short gap during which a new shader is uploaded before the monitor displays it.
If you would like to write your own shaders (and emulate them), take a look at the "sw" folder in the repository: https://github.com/mole99/tt06-tiny-shader
If you send me your shader code, I will try it out on the real hardware 
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GIF
I'm going to start a regular weekly stream about #opensource silicon. Topics will include design, verification, #fpga, openlane, formal, #tinytapeout, #ASIC bringup, chip validation.
If you're interested, please let me know what days / times work for you:
We now have some limited edition chips mounted in epoxy resin! Each chip is numbered and comes with a GDS render and details of the designs it contains.
Own some open source #ASIC history and support me in my ongoing efforts to lower the barrier to entry into this exciting and important field.
MPW1 https://store.tinytapeout.com/products/Bare-die-cast-in-resin-MPW1-p716799289
MPW2 https://store.tinytapeout.com/products/Bare-die-cast-in-resin-MPW2-p716799290
MPW3 https://store.tinytapeout.com/products/Bare-die-cast-in-resin-MPW3-p716785817
MPW4 https://store.tinytapeout.com/products/Bare-die-cast-in-resin-MPW4-p716799291
MPW5 https://store.tinytapeout.com/products/Bare-die-cast-in-resin-MPW5-p716799292
After seeing @matthewvenn 's post, I had to try it out for myself: Running uLinux on the KianV RISC-V SoC on Tiny Tapeout 06 ️
First step: Connecting the QSPI Pmod to the bidirectional port of the demo board. This gives the system 128Mbit Flash and PSRAM (pseudo SRAM).
The next steps can be carried out entirely from within the browser.
I just booted uLinux on #TinyTapeout 6!
Very easy to use flashing tool by Uri made it easy to test Hirosh's SoC!
Also big thanks to @mike & @mole99 for the PMOD we're using with designs that need external memory.
My Tiny Tapeout 06 board and chip have arrived!
Finally I can play with my design "Tiny Shader" on real silicon 
I also ordered the QSPI and Audio Pmod, which will come in handy for future projects 
Now, does my design work as expected?
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@calisti @pluto @jak2k @alexis_roussel also it ridicules #ASIC use as well it's #centralization!
- There are less people in control of #Bitcoin's Hashrate than there are people in control of #PrintingPresses and equipment for #Euro banknotes.
Infosec.SpaceKevin Karhan :verified: (@kkarhan@infosec.space)@duco@norden.social @alexis_roussel@piratenpartei.social what makes #Bitcoin the real #shitcoin (along with basically everything that isn't #Monero) is that it's not only #PoW (#ProofOfWork) but also basically #ASIC-based, so that means literal metric tons of #eWaste get created every year producing those.
- And since ASICs ain't like #CPU|s, #GPU|s & #FPGA|s, one can't even #reuse & #upcycle them for different workloads (like #Rendering and general-purpose #Compute) as they are absolutely inflexible in their use-case.
Replied in thread
@duco @alexis_roussel what makes #Bitcoin the real #shitcoin (along with basically everything that isn't #Monero) is that it's not only #PoW (#ProofOfWork) but also basically #ASIC-based, so that means literal metric tons of #eWaste get created every year producing those.