W65C832 in an FPGA

Link: https://www.mikekohn.net/micro/w65c832_fpga.php
Discussion: https://news.ycombinator.com/item?id=43658417

I'm super happy that my latest chip Greyhound has been accepted for production!
It was designed with open source EDA tools and the IHP Open Source PDK.

Find out more here: https://github.com/mole99/greyhound-ihp

And down below

#ASIC #FPGA# OpenSource

The Spade Hardware Description Language - Spade is an open-source hardware description language (HDL) developed at Linköping... - https://hackaday.com/2025/04/13/the-spade-hardware-description-language/ #hardwaredescriptionlanguage #spadelanguage #hardware #verilog #fpga #asic #vhdl #hdl

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

New PCB rework!

This time instead of soldering on the track I used a short coil wire so the job is cleaner!

Applying the rework-fix on board #2 proved that board #1 io expander was burnt!

All (SPI+io expander) is good now on board #2 :)

#RC2014 Emulation for
#MiST and #SiDi #FPGA
available at
https://www.atari-forum.com/viewtopic.php?t=44842

The PCB rework of this sunday afternoon :)

It went well!

FYI I don't have binocular nor a good soldering iron.

Had to scratch the track, unsolder the very small resistor, re-solder it on the track (from parallel to series).

It's a bit dirty I agree but it's done and it works!

Triangle rasterisation is surprisingly complex. There are multiple approaches and decisions to make on which pixels to include. As part of testing my Earthrise #FPGA graphics engine, I've created visual tests to complement more automated testing.

While working on my #FPGA projects I've collected quotes and ideas I've found throught-provoking or inspiring. (1/n)

"A simple system, designed from scratch, sometimes works... A complex system that works is invariably found to have evolved from a simple system that worked." — John Gall

What do we know about the Gowin GW5A #FPGA (GW5AT-LV60P484A) found on the Tang Console?

Board pricing looks reasonable, but I'm naturally concerned about open-source support. I did see some discussion at Project Apicula last year: https://github.com/YosysHQ/apicula

Drop in #FPGA replacements for faulty #SNES cpus? Hell yeah. #RetroGaming https://www.timeextension.com/news/2025/04/soon-dead-snes-consoles-will-be-resurrected-by-fpga-technology

Heute wird mal wieder das #MiSTer #FPGA Board auf den aktuellsten Stand gebracht. Das lag jetzt jahrelang nur in der Gegend herum. Wird also Zeit, dass ich es mal wieder aus der Mottenkiste hole. Ich meine, ich hätte es mir 2019 gekauft, als die Preise noch nicht so hoch waren.

Reconfigurable FPGA for Single Photon Measurements - Detecting single photons can be seen as the backbone of cutting-edge applications ... - https://hackaday.com/2025/03/30/reconfigurable-fpga-for-single-photon-measurements/ #experiment #measure #webinar #photon #fpga

Thesis: Hardware-Assisted Software Testing and Debugging for Heterogeneous Computing

#oneAPI #FPGA #Python

https://hgpu.org/?p=29840

New computer on MiST! Amstrad PCW arrives to Sidi and the core works perfectly!

https://github.com/tdelage26/SiDi-FPGA/tree/master/Cores/Computer/AmstradPCW

Minimig (Amiga OCS-ECS-AGA-RTG) core has been updated on MiST now with a stable version after several years

=== minimig_mist_rtg_250324.rbf ===

- Major update, refer to git history for changes

https://github.com/minimig-dev/MinimigAGA-MiST-TC64/compare/56d378a...stable

Download it here:

https://github.com/mist-devel/mist-binaries/tree/master/cores/minimig-aga

Oh hell yes, ARP and ICMP ping request reply works on my #fpga ethernet stack!

Good news open-source #FPGA fans, there's a new release of nextpnr (place and route) from @yosyshq. The release notes mention "Numerous improvements to Gowin support": https://github.com/YosysHQ/nextpnr/releases/tag/nextpnr-0.8