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#instructionsetarchitecture

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IT News<p>Checking In On the ISA Wars and Its Impact on CPU Architectures - An Instruction Set Architecture (ISA) defines the software interface through which... - <a href="https://hackaday.com/2025/03/18/checking-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">hackaday.com/2025/03/18/checki</span><span class="invisible">ng-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/</span></a> <a href="https://schleuss.online/tags/instructionsetarchitecture" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>instructionsetarchitecture</span></a> <a href="https://schleuss.online/tags/microcontrollers" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>microcontrollers</span></a> <a href="https://schleuss.online/tags/currentevents" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>currentevents</span></a> <a href="https://schleuss.online/tags/hardware" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>hardware</span></a> <a href="https://schleuss.online/tags/interest" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>interest</span></a> <a href="https://schleuss.online/tags/cpuisa" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>cpuisa</span></a> <a href="https://schleuss.online/tags/risc" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>risc</span></a>-v <a href="https://schleuss.online/tags/x86_64" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>x86_64</span></a> <a href="https://schleuss.online/tags/mips" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>mips</span></a> <a href="https://schleuss.online/tags/arm" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>arm</span></a></p>
Jure Repinc :linux: :kde:<p>RISC-V Vector Extension overview<br>🔗&nbsp;<a href="http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">http://</span><span class="ellipsis">0x80.pl/notesen/2024-11-09-ris</span><span class="invisible">cv-vector-extension.html</span></a></p><p>"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.<br>[…]<br>The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load &amp; store operations."</p><p><a href="https://mstdn.io/tags/RISCV" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>RISCV</span></a> <a href="https://mstdn.io/tags/RISC_V" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>RISC_V</span></a> <a href="https://mstdn.io/tags/RVV" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>RVV</span></a> <a href="https://mstdn.io/tags/ComputerArchitecture" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>ComputerArchitecture</span></a> <a href="https://mstdn.io/tags/ISA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>ISA</span></a> <a href="https://mstdn.io/tags/InstructionSetArchitecture" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>InstructionSetArchitecture</span></a> <a href="https://mstdn.io/tags/CPU" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPU</span></a> <a href="https://mstdn.io/tags/CPUs" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPUs</span></a> <a href="https://mstdn.io/tags/processor" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>processor</span></a> <a href="https://mstdn.io/tags/processors" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>processors</span></a></p>
Jure Repinc :linux: :kde:<p>RISC-V State of the Union — current highlights and roadmap of RISC-V by RISC-V's chief architect<br>🎞 <a href="https://yewtu.be/watch?v=_oLVPFQvJbI" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="">yewtu.be/watch?v=_oLVPFQvJbI</span><span class="invisible"></span></a><br>Slides: <a href="https://riscv-europe.org/summit/2024/media/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">riscv-europe.org/summit/2024/m</span><span class="invisible">edia/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf</span></a></p><p><a href="https://mstdn.io/tags/RISCV" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>RISCV</span></a> <a href="https://mstdn.io/tags/RISC" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>RISC</span></a> <a href="https://mstdn.io/tags/CPU" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPU</span></a> <a href="https://mstdn.io/tags/CPUs" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPUs</span></a> <a href="https://mstdn.io/tags/architecture" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>architecture</span></a> <a href="https://mstdn.io/tags/ComputerArchitecture" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>ComputerArchitecture</span></a> <a href="https://mstdn.io/tags/processor" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>processor</span></a> <a href="https://mstdn.io/tags/processors" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>processors</span></a> <a href="https://mstdn.io/tags/ISA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>ISA</span></a> <a href="https://mstdn.io/tags/InstructionSetArchitecture" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>InstructionSetArchitecture</span></a> <a href="https://mstdn.io/tags/hardware" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>hardware</span></a></p>
IT News<p>Software Defined… CPU? - Everything is better when you can program it, right? We have software-defined radi... - <a href="https://hackaday.com/2021/07/19/software-defined-cpu/" rel="nofollow noopener noreferrer" target="_blank"><span class="invisible">https://</span><span class="ellipsis">hackaday.com/2021/07/19/softwa</span><span class="invisible">re-defined-cpu/</span></a> <a href="https://schleuss.online/tags/instructionsetarchitecture" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>instructionsetarchitecture</span></a> <a href="https://schleuss.online/tags/instructionset" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>instructionset</span></a> <a href="https://schleuss.online/tags/computerhacks" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>computerhacks</span></a> <a href="https://schleuss.online/tags/news" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>news</span></a> <a href="https://schleuss.online/tags/cpu" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>cpu</span></a> <a href="https://schleuss.online/tags/isa" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>isa</span></a> <a href="https://schleuss.online/tags/x86" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>x86</span></a></p>
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